The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2004
Filed:
Aug. 07, 2002
Yasushi Wada, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A logic optimization device refers to hierarchical circuit-design descriptions representing multiple layers of an integrated circuit, and decides whether or not each output terminal at each lower layer is connected with its upper layer. If an output terminal at a lower layer has been decided to be unconnected with its upper layer, the logic optimization device deletes from the hierarchical circuit-design descriptions an information part describing the output terminal, and deletes from the hierarchical circuit-design descriptions an information part describing an element at the lower layer connected with the deleted output terminal, thereby producing a gate-level net-list of an integrated circuit without ineffectual elements.