Semiconductor storage device

Abstract

A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit ( ) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed. And, for late writing at the time of the next write request, the address and the data are taken into register circuits ( ) upon the rising edge of the write enable signal (/WE).