The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2004

Filed:

Oct. 04, 2002
Applicant:
Inventors:

Richard M. Fastow, Cupertino, CA (US);

Yue-Song He, San Jose, CA (US);

Nga-Ching Wong, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18234 ;
U.S. Cl.
CPC ...
H01L 2/18234 ;
Abstract

The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.


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Fastow, Richard. (2004). Method for reducing drain induced barrier lowering in a memory device (U.S. Patent No. 6833297). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6833297

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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