The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6832328 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 14, 2004

Filed:

May. 08, 2001
Applicant:
Inventor:

Satoru Kishimoto, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 ;
U.S. Cl.
CPC ...
G06F 1/04 ;
Abstract

An object of the present invention is to enable precise and easy adjustment of clock skew. A clock distribution circuit is designed and the placement and routing of the entire chip including the clock distribution circuit follows. Then the clock skew value is calculated and whether the calculated clock skew exceeds a target value is checked. When the clock skew exceeds the target value, the outputs of some driver elements are disconnected or connected to adjust the clock skew. The steps disconnecting or connecting the outputs of the drivers are repeated until the clock skew becomes equal to or smaller than the target value.


Find Patent Forward Citations

Kishimoto, Satoru. (2004). Placement and routing method for optimizing clock skew in clock distribution circuit (U.S. Patent No. 6832328). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6832328

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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