The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6831316 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 14, 2004

Filed:

Mar. 19, 2002
Applicant:
Inventors:

Hideyuki Matsuoka, Nishi-Tokyo, JP;

Takeshi Sakata, Hino, JP;

Shinichiro Kimura, Kunitachi, JP;

Toshiaki Yamanaka, Iruma, JP;

Tsuyoshi Kachi, Kokubunji, JP;

Tomonori Sekiguchi, Kokubunji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 4/700 ; H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 4/700 ; H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
Abstract

An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.


Find Patent Forward Citations

Matsuoka, Hideyuki. (2004). Semiconductor memory device and method of manufacturing the same (U.S. Patent No. 6831316). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6831316

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