The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2004

Filed:

Jun. 09, 1999
Applicant:
Inventors:

Hiroshi Ito, Atsugi, JP;

Akira Yamagiwa, Naka-gun, JP;

Nobuaki Ejima, Hadano, JP;

Ryoichi Kurihara, Hadano, JP;

Masakazu Sakaue, Atsugi, JP;

Yasuhiro Uemura, Hadano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 ;
U.S. Cl.
CPC ...
G06F 9/455 ;
Abstract

Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis. Also disclosed here is an upgraded module structure permitting a multiple-stage module setup together with an advanced cooling structure for modules.


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