Semiconductor memory device and bit line sensing method thereof

Abstract

In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.