The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2004
Filed:
Mar. 05, 2003
John Michael Hergenrother, Short Hills, NJ (US);
Muhammed Ayman Shibib, Wyomissing, PA (US);
Shuming Xu, Schnecksville, PA (US);
Zhijian Xie, Allentown, PA (US);
Agere Systems, Inc., Allentown, PA (US);
Abstract
A diffused MOS device comprises one or more strained silicon portions formed in a carrier transit path of the DMOS device. The one or more strained silicon portions may comprise a layer of strained silicon, generally formed above a layer of lattice mismatch material such as silicon germanium or silicon carbide. The carrier transit path is at least partially defined by a body of the DMOS device, and may also include other regions, such as a diffusion area, channel region, or accumulation region. The one or more strained silicon portions may be formed only in selected regions of the DMOS device or may be formed as a layer throughout. The one or more strained silicon portions may be formed through patterning of a hard mask, forming a lattice mismatch layer, forming a strained silicon layer, and removing the hard mask. Trenches may also be formed prior to forming the lattice mismatch material on the patterned hard mask.