The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2004

Filed:

Mar. 26, 1999
Applicant:
Inventors:

Byoung-taek Lee, Seoul, KR;

Ki-hoon Lee, Kyungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A method of manufacturing a capacitor includes sequentially forming a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer over a semiconductor substrate. A first post-annealing of the substrate is performed under an inert atmosphere at a first temperature, and then a second post-annealing is performed at a second temperature. The first and second post annealings can be performed after forming the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination thereof, as long as the second post-annealing is performed after the first post-annealing. The post-annealings are not necessarily performed in a same place or stage. The first temperature may be about 600° C. to 900° C., and the second temperature about 100° C. to 600° C. As a result, the dielectric constant of the high dielectric layer is increased, and leakage current is reduced.


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