The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2004

Filed:

Sep. 04, 2002
Applicant:
Inventors:

Chan-Hoon Park, Seoul, KR;

Bong-Su Cho, Sungnam, KR;

Hyun-Tae Kang, Yongin, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A semiconductor wafer overlay correction method for an exposure process in a semiconductor fabricating stepper incorporates variations in equipment characteristics with time. The wafer overlay correction method includes measuring an overlay error correction value of a semiconductor wafer that is exposed by the stepper, calculating an overlay error correction value by summing the measured overlay error correction value, a variation in the stepper characteristics that is obtained through an empirical characterization of input changes, and a weighting value obtained from a predetermined plurality of wafer lots, and providing the calculated overlay error correction value to the semiconductor fabricating stepper to control an exposure process of a subsequent wafer lot.


Find Patent Forward Citations

Park, Chan-Hoon. (2004). Method for automatically correcting overlay alignment of a semiconductor wafer (U.S. Patent No. 6826743). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6826743

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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