Smart cache

Abstract

A cache architecture ( ) for use in a processing includes a RAM set cache for caching a contiguous block of main memory ( ). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register ( ) defines a starting address for the contiguous block of main memory ( ). The data array ( ) associated with the RAM set may be filled on a line-by-line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array ( ) when the starting address is loaded into the register ( ). As addresses are received from the processing core, hit/miss logic ( ) the starting address register ( ), a global valid bit ( ), line valid bits ( ) and control bits ( ) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory ( ). The hit/miss logic ( ) also determines whether a line should be loaded into the RAM set data array ( ) or in the associated cache.