The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2004

Filed:

Jun. 20, 2003
Applicant:
Inventor:

Hideo Akiyoshi, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/017 ;
U.S. Cl.
CPC ...
H03K 3/017 ;
Abstract

A pulse generation circuit generates an output pulse that is set to its activated level in response to a leading edge of a set pulse. The pulse generation circuit comprises an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, for propagating the set pulse and driving the first output transistor; a second inverter array, for propagating a reset pulse, and for driving the second output transistor. To prevent the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, being driven in response to the reset pulse propagating through the second inverter array.


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