The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 2004

Filed:

Aug. 15, 2003
Applicant:
Inventor:

Steven L. Haehn, Fort Collins, CO (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/903 ;
U.S. Cl.
CPC ...
H03K 1/903 ;
Abstract

A system is provided for yield enhancement in programmable logic. The system includes first and second random combinational logic, first and second sets of IP logic blocks, and first and second BIST/MUX controllers. The first controller is electrically connected between the first logic and each of the blocks in the first set and electrically connected between each of the blocks in the first set and the second logic. The second controller is connected in the same manner with respect to the second set of blocks. The controllers are configured to test the blocks for functionality or non-functionality, to identify functional ones of the blocks and to provide electrical connections between a predetermined number of the functional blocks and the first and second logic.


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