Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices

Abstract

A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices in an integrated circuit comprising flash memory devices and both thick and thin gate transistor devices. The method begins by forming a tunnel oxide layer over a semiconductor substrate for the formation of the flash memory devices (step ). A mask is formed over the thin gate transistor devices to inhibit formation of a thick gate oxide layer for the formation of the thick gate transistor devices (step ). The mask reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer before forming a thin oxide layer for the thin gate transistor devices