The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2004

Filed:

Mar. 13, 2003
Applicant:
Inventor:

Michael Achter, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A sense amplifier circuit. Specifically, a sample and hold sense amplifier circuit that is capable of sampling and holding a reference voltage comprises a reference voltage sampler circuit coupled to a cross-coupled inverter latch. The reference voltage sampler circuit is coupled to a bitline associated with a memory cell. The reference voltage is sampled from a precharge voltage taken off the bitline, and is used to read a state on a memory cell. The cross-coupled inverter latch is also coupled to the bitline, and is used for amplifying a voltage difference between an output voltage from the cross-coupled inverter latch and the reference voltage. The output voltage is based on a static bitline voltage from the bitline.

Published as:

Find Patent Forward Citations

Achter, Michael. (2004). Apparatus and method for a sense amplifier circuit that samples and holds a reference voltage (U.S. Patent No. 6819612). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6819612

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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