The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2004
Filed:
Jan. 06, 2003
Kung-Hong Lee, Ping-Tung Hsien, TW;
Ching-Hsiang Hsu, Hsin-Chu, TW;
Ya-Chin King, Tao-Yuan Hsien, TW;
Shih-Jye Shen, Hsin-Chu, TW;
Ming-Chiu Ho, Hsin-Chu, TW;
eMemory Technology Inc., Hsin-Chu, TW;
Abstract
An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and is used for storing data. A second N-type doped region is located inside the P-type substrate adjacent to the first gate. A second gate is located on the P-type substrate and adjacent to the second N-type doped region and acts as a select gate. A third N-type doped region is located inside the P-type substrate adjacent to the second gate.