The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2004

Filed:

Feb. 03, 2003
Applicant:
Inventors:

Masayuki Konishi, Tokyo, JP;

Takehiko Shimomura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 ;
U.S. Cl.
CPC ...
G11C 5/06 ;
Abstract

A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN to PN ) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW ) and a switch (SW ). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN ) and the fifth pin (PN ).


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