The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6819579 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 16, 2004

Filed:

Apr. 22, 2003
Applicant:
Inventors:

Kwo-Jen Liu, San Jose, CA (US);

Hsin-Shih Wang, Fremont, CA (US);

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/500 ;
U.S. Cl.
CPC ...
G11C 1/500 ;
Abstract

A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM), cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.


Find Patent Forward Citations

Liu, Kwo-Jen. (2004). Integrated content addressable memory architecture (U.S. Patent No. 6819579). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6819579

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