The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2004

Filed:

Dec. 12, 2002
Applicant:
Inventors:

Minh Van Ngo, Fremont, CA (US);

Christine Hau-Riege, Fremont, CA (US);

Steve Avanzino, Cupertino, CA (US);

Robert A. Huertas, Hollister, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/1302 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/1302 ;
Abstract

The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH and N , ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH plasma diluted with N , shutting off the power, discontinuing the N flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.


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