The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2004
Filed:
Nov. 19, 2002
Norikatsu Takaura, Kokubunji, JP;
Riichiro Takemura, Tokyo, JP;
Hideyuki Matsuoka, Nishitokyo, JP;
Shinichiro Kimura, Kunitachi, JP;
Hisao Asakura, Ome, JP;
Ryo Nagai, Mizuho, JP;
Satoru Yamada, Ome, JP;
Other;
Abstract
A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp and nw is L the width between active areas nwp and nw is L and the width between active areas nwp and nwp is L (L −L ), (L −L ), and (L −L ) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L L and L can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.