The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2004
Filed:
May. 20, 2002
Harold J. Levy, Los Gatos, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A computer implemented method of producing a reduced order model of an electronic circuit to model the connection of two or more circuits. Arnoldi reduced order models for nodes of circuits to be interconnected may be computed. A set of modified nodal analysis matrices for the combination of the two circuits may be constructed. A rank one update may be applied to the modified set of nodal analysis matrices to produce a reduced order model of the combined electronic circuits. In this novel manner, a reduced order model for a combination of circuits may be produced from the individual reduced order models of the individual circuits without the need to recompute the reduced order models of the original circuits, and without the need of the original parasitic network models. The resulting reduced order model may be used in a variety ways consistent with well known uses of such matrices within the field of electronic design automation.