The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2004
Filed:
Jul. 10, 2002
Applicant:
Inventors:
Alexander Tetelbaum, Hayward, CA (US);
Maad A. Al-Dabagh, Sunnyvale, CA (US);
Duc Van Huynh, San Jose, CA (US);
Ruben Molina, Jr., San Ramon, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06G 7/62 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06G 7/62 ;
Abstract
A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.