Multiport memory circuit composed of 1tr-1c memory cells

Abstract

A multiport memory circuit includes an access address selecting circuit for asserting a word line of an address that is subjected to write operation or read operation; refresh circuits, each of which is asserted when data of a corresponding memory cell is at an “L” level to rewrite the “L” level data back to the memory cell via a read bit line; a write/read bit-line selecting circuit for selecting, under the control of a write/read switching circuit, one of transferring write data to the bit lines and transferring data on the bit lines to the sense amplifiers; and a frequency multiplier for generating an internal clock signal with a frequency equal to or greater than double the higher frequency of the write clock signal and read clock signal. It can reduce the area of the memory cells and hence the chip size.