The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 26, 2004
Filed:
Oct. 22, 2002
Applicant:
Inventors:
Shigeru Yamaoka, Hyogo, JP;
Shigehiro Kuge, Hyogo, JP;
Assignee:
Renesas Technology Corp., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract
This DDR SDRAM includes a test mode entry signal generation circuit which sets a test mode entry signal at “H” level in accordance with a consecutive input of a first command, a second command, a test mode entry set command, a third command and a test mode register set command synchronously with a rising edge of a clock signal. This enables the DDR SDRAM to enter a test mode without using a high voltage. The DDR SDRAM can, therefore, enter the test mode even if it is incorporated into a registered DIMM.