The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 26, 2004

Filed:

Jul. 11, 2002
Applicant:
Inventor:

Henry Wei-Ming Chung, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ;
Abstract

A method of forming dual salicides for integrated circuits. A mask layer is formed over a substrate having a first transistor and a second transistor thereon. The top surface of the first transistor's gate is higher than that of the second transistors' gate. The mask layer is patterned to expose the top surface of the second transistor's gate, source and drain. First metal suicides are formed respectively on the top surfaces of the second transistor's gate, source and drain. A dielectric layer is formed over the substrate, and the top surface of the dielectric layer is higher than that of the first transistor's gate. The dielectric layer, higher than the top surface of the second transistor's gate, is removed to expose the top surfaces of the first and the second transistors' gates. A second metal silicide is formed on the top surface of the first transistor's gate.


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