The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 19, 2004

Filed:

Apr. 22, 2002
Applicant:
Inventors:

Keith D. Gann, Tustin, CA (US);

Douglas M. Albert, Yorba Linda, CA (US);

Assignee:

Irvine Sensors Corporation, Costa Mesa, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/3495 ; H01L 2/148 ; H01R 4/300 ; H05K 5/02 ;
U.S. Cl.
CPC ...
H01L 2/3495 ; H01L 2/148 ; H01R 4/300 ; H05K 5/02 ;
Abstract

Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.


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