The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6806148 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 19, 2004

Filed:

May. 28, 2003
Applicant:
Inventors:

Kyu Hyun Choi, Cupertino, CA (US);

Sheau-suey Li, Cupertino, CA (US);

Assignee:

O2IC, Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A method of forming an integrated circuit, includes, in part: forming trench isolation in a semiconductor substrate, forming a first well between the trench isolation, forming a second well above the first well, forming a first oxide layer above a first portion of the second well, forming a first dielectric layer above the first oxide layer, forming a first polysilicon gate layer above the first dielectric layer, forming a second dielectric layer above the first polysilicon layer, forming a first spacer above the body region and adjacent the first polysilicon layer, forming a second oxide layer above a second portion of the second well not covered by the first spacer, forming a second polysilicon gate layer above the second oxide layer, the first spacer and a portion of the second dielectric layer, and forming a second spacer to define source and drain regions.


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Choi, Kyu. (2004). Method of manufacturing non-volatile memory device (U.S. Patent No. 6806148). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6806148

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