Flash memory architecture with page mode erase using nmos and pmos row decoding scheme

Abstract

A flash memory with a page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry. The global decoder is located outside of the sectors and provides global signals to all sectors via the local circuitry, thus saving area.