The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2004
Filed:
Jan. 31, 2003
Applicant:
Inventors:
Kenichi Yasuda, Hyogo, JP;
Hironori Iga, Hyogo, JP;
Assignee:
Renesas Technology Corp., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/900 ; H03K 5/153 ; H03K 5/22 ;
U.S. Cl.
CPC ...
H03K 1/900 ; H03K 5/153 ; H03K 5/22 ;
Abstract
Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT , OUT therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT and OUT are combined in-phase.
Yasuda, Kenichi. (2004). Input buffer circuit with constant response speed of output inversion (U.S. Patent No. 6803792). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6803792
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