The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6803782 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 12, 2004

Filed:

Mar. 21, 2003
Applicant:
Inventors:

John Conrad Koob, Edmonton, AB, CA;

Raymond Jit-Hung Sung, Wilmington, MA (US);

Tyler Lee Brandon, Sherwood Park, AB, CA;

Duncan George Elliot, Edmonton, AB, CA;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ;
U.S. Cl.
CPC ...
H03K 1/9177 ;
Abstract

A column redundancy architecture for arrayed parallel processor devices is disclosed. In particular, daisy chained communication between processing elements is preserved after defective memory columns and their associated processing elements are disabled, by setting a bypass circuit within the processing element to be disabled. An address remapping circuit ensures that spare memory columns and associated processing elements replacing the defective memory columns and processing elements can be addressed in a linear column order. The column redundancy architecture is flexible as it permits replacement of arbitrary numbers of series adjacent processing elements as well as non adjacent processing elements with a minimal impact on device performance.


Find Patent Forward Citations

Koob, John. (2004). Arrayed processing element redundancy architecture (U.S. Patent No. 6803782). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6803782

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