The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 12, 2004

Filed:

Jun. 25, 2003
Applicant:
Inventors:

Dae-Joung Kim, Suwon-si, KR;

Seok-Hwan Oh, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/176 ;
U.S. Cl.
CPC ...
H01L 2/176 ;
Abstract

In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region of a semiconductor substrate and simultaneously in a first mark formation region of the semiconductor substrate. A second pattern for the semiconductor device is formed on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously in a second mark formation region of the semiconductor substrate. The first and second patterns in the first and second mark formation regions, respectively, are inspected for misalignments using overlay marks formed to have shapes and sizes identical to those of real patterns in the semiconductor device formation region of the semiconductor substrate. By measuring misalignments of real patterns using the overlay marks, overlay mismatch between the semiconductor device formation region and the overlay mark may be prevented.


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