The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 12, 2004
Filed:
Feb. 10, 2003
Chong Jen Hwang, Hsinchu, TW;
Macronix International Co., Ltd., Hsinchu, TW;
Abstract
A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a first layer of polysilicon in the array portion and in the non-array portion; covering the first layer of polysilicon with a layer of silicon nitride; using two masks for gate electrode formation in a first layer of polysilicon and bit line implant processes; depositing a dielectric material among the gate electrode structures to fill gaps among the gate structures; planarizing the deposited oxide; removing said layer of silicon nitride and applying a second layer of polysilicon material; patterning wordlines in the array portion over said gate electrode structures, and transistor gate structures in said non-array portion, and applying LDD, silicide and other logic circuit processes.