The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 05, 2004
Filed:
Aug. 06, 2002
Steven T. Peake, Warrington, GB;
Georgios Petkos, Stockport, GB;
Philip Rutter, Stockport, GB;
Raymond J. Grover, Didsbury, GB;
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer ( ), for example of polysilicon gate material, extends on an intermediate insulating layer ( ) over a higher-doped (P+) end region ( ) of the channel-accommodating region ( ). This insulating layer ( ) comprises an area ( ) of a trench-etch mask ( ), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer ( ). A window ( ) extends through the trench-etch mask ( ) at a location where an end trench ( ) extends into the P+ region ( ). The end trench ( ) is an extension of the insulated gate trench ( ) into the P+ region ( ) and accommodates an extension ( ) of the trench-gate ( ). The conductive layer ( ) is connected to the trench-gate extension ( ) via the window ( ). The lateral extent of the conductive layer ( ) terminates in an edge ( ) that is defined on the trench-etch mask ( ).