The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 28, 2004
Filed:
May. 16, 2002
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The input buffer includes switching circuitry driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The switching circuitry includes components to prevent damage to low voltage transistors used in the output buffer should the output pad (PAD) voltage exceed VDD, or should charge buildup occur on the common well of PMOS transistors used in the output buffer exceed VDD.