The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 28, 2004

Filed:

Sep. 16, 2002
Applicant:
Inventors:

Jean Yee-Mei Yang, Sunnyvale, CA (US);

Yider Wu, Campbell, CA (US);

Zhizheng Liu, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.


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Yang, Jean Yee-Mei. (2004). Methods for fabricating and planarizing dual poly scalable sonos flash memory (U.S. Patent No. 6797565). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6797565

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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