Non volatile memory and data processor

Abstract

The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC through QPCm) to each of main bit lines (MB through MBm) during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB through LBkm) are respectively discharged by discharge elements (QD through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.