The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2004

Filed:

Apr. 14, 2000
Applicant:
Inventors:

Dung-Ching Perng, San Jose, CA (US);

Yauh-Ching Liu, Sunnyvale, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/18242 ;
Abstract

A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.


Find Patent Forward Citations

Perng, Dung-Ching. (2004). Formation of novel dram cell capacitors by integration of capacitors with isolation trench sidewalls (U.S. Patent No. 6794698). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6794698

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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