The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6789137 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 07, 2004

Filed:

Feb. 12, 2003
Applicant:
Inventor:

Takashi Itoh, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/314 ;
U.S. Cl.
CPC ...
G06F 1/314 ;
Abstract

A semiconductor memory device includes an address buffer, a clock buffer, a control signal buffer, a control circuit, a mode register, a memory cell array, a signal select circuit, a DLL, an I/O buffer and a QS buffer. The mode register provides a signal at H- or L-level to the signal select circuit. The signal select circuit selects a data strobe signal sent from an I/O terminal in accordance with the signal at L-level, and provides it to the QS buffer. The signal select circuit selects a clock sent from an I/O terminal in accordance with the signal at H-level, and provides it to the QS buffer.


Find Patent Forward Citations

Itoh, Takashi. (2004). Semiconductor memory device allowing reduction of i/o terminals (U.S. Patent No. 6789137). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6789137

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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