Semiconductor memory device with shortened connection length among memory block, data buffer and data bus

Abstract

There is provided a semiconductor memory device including eight memory blocks to , first data bus , and second data bus . The eight memory blocks are arranged at respective eight of the total nine areas to defined in a three rows by three columns matrix except for a center area . A first data bus linearly extends between memory blocks in the first and second row of the matrix. A second data bus linearly extends between memory blocks in the second and third row of the matrix. The eight memory blocks includes a first group of the four memory blocks arranged adjacent the first data bus and connected to the first data bus and a second group of the four memory blocks arranged adjacent the second data bus and connected to the second data bus.