Statistical counters in high speed network integrated circuits

Abstract

Architecture and corresponding methods share resources and synchronize counters in high-speed network integrated circuits. The architecture has at least one counter group comprising several registers, each with two ports. One port receives networking events (e.g., receipt of an-error packet, transmission of a good packet, etc.) via a tri-state bus. The registers in each counter group use a shared hardware memory element, which adds the events for each counter group. The second port is available for asynchronous external read accesses via a second tri-state bus. The architecture synchronizes read requests with events such that read accesses occur during gaps in events. The registers are assigned to several mutually exclusive counter groups such that no two registers in the counter group increment in a basic clock cycle.