The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6780748 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 24, 2004

Filed:

Jul. 30, 2002
Applicant:
Inventors:

Yoshihide Yamaguchi, Fujisawa, JP;

Hiroyuki Tenmei, Yokohama, JP;

Hiroshi Hozoji, Hitachiota, JP;

Naoya Kanda, Fujisawa, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01R 4/316 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01R 4/316 ;
Abstract

In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines that connect the bonding pads and bump pads of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.


Find Patent Forward Citations

Yamaguchi, Yoshihide. (2004). Method of fabricating a wafer level chip size package utilizing a maskless exposure (U.S. Patent No. 6780748). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6780748

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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