The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2004

Filed:

Sep. 23, 2002
Applicant:
Inventors:

Mark G. Johnson, Los Altos, CA (US);

Thomas H. Lee, Cupertino, CA (US);

Vivek Subramanian, Menlo Park, CA (US);

Paul Michael Farmwald, Portola Valley, CA (US);

Assignee:

Matrix Semiconductor, INC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/1336 ; H01L 3/1119 ;
Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.


Find Patent Forward Citations

Johnson, Mark. (2004). Vertically stacked field programmable nonvolatile memory and method of fabrication (U.S. Patent No. 6780711). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6780711

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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