The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2004
Filed:
Feb. 09, 2001
Shinichi Muramatsu, Tokyo, JP;
Yasushi Minagawa, Tokyo, JP;
Fumihito Oka, Tokyo, JP;
Susumu Takahashi, Chiba, JP;
Yoshiaki Yazawa, Tokyo, JP;
Hitachi Cable, Ltd., Tokyo, JP;
Abstract
Concave and convex are formed on the substrate , the amorphous silicon layer is formed on the metallic catalyst dispersed and arranged in a dotted shape in the concave portion of the concave and convex, the crystal phases having respective orientations from the metallic catalyst are grown, further the crystal phases are integrated with each other by continuing heat treatment and the polycrystalline silicon layer is formed. A crystalline silicon semiconductor device and its method for fabrication which are costly advantageous and capable of efficiently forming the polycrystalline silicon layer of a predetermined thickness needed as a semiconductor device are provided. Moreover, on the substrate , the polycrystalline silicon layer oriented on the face (111), the metallic catalyst consisted of Ni, the polycrystalline silicon layer are formed in turn, further, after on which the amorphous silicon layer of the predetermined thickness is formed, Ni element is diffused within the amorphous silicon layer from the metallic catalyst layer by performing heat treatment, and thereby crystallizing the amorphous silicon layer into the polycrystalline silicon layer