Semiconductor memory device switchable to twin memory cell configuration

Abstract

A row address decoder of a semiconductor memory device generates internal row address signals RAD< and /RAD< > by switching most significant bit and least significant bit of row address signals RA< > and /RA< > that correspond to address signals A to A , respectively. In a twin cell mode, the least significant bits RAD< > and /RAD< > of the internal row address signals corresponding to the most significant bits RA< > and /RA< > of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.