The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6774442 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 10, 2004

Filed:

Jul. 20, 2001
Applicant:
Inventors:

Kiyoshi Hayashi, Tokyo, JP;

Yasuo Inoue, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/978 ; H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 2/978 ; H01L 3/1113 ;
Abstract

Provided are a semiconductor device comprising a polymetal gate electrode that can prevent formation of a silicide layer at the interface between metal and conductive silicon and also exhibit low resistance property and ohmic property, and a method for manufacturing the same. Specifically, a polymetal gate electrode is formed via a gate insulating film ( ), e.g., an oxide film, on a semiconductor substrate ( ), e.g., a silicon substrate. The polymetal gate electrode has such a structure that a conductive silicon film ( ), e.g., a poly-Si film, a silicide film ( ), e.g., a WSi film, a barrier film ( ), e.g., a WSiN film, and a metal film ( ), e.g., a W film, are stacked over the semiconductor substrate ( ) in the order named.


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Hayashi, Kiyoshi. (2004). Semiconductor device and cmos transistor (U.S. Patent No. 6774442). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6774442

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