The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6774042 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 10, 2004

Filed:

Feb. 26, 2002
Applicant:
Inventors:

Chia-Der Chang, Hsin-Chu, TW;

Yi-Tung Yen, Hsin-Dam, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/131 ; H01L 2/14763 ; H01L 2/1311 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/131 ; H01L 2/14763 ; H01L 2/1311 ;
Abstract

A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.


Find Patent Forward Citations

Chang, Chia-Der. (2004). Planarization method for deep sub micron shallow trench isolation process (U.S. Patent No. 6774042). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6774042

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