The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
Oct. 17, 2002
Wen-chou Vincent Wang, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Provided are flip chip device assembly methods that integrate the solder joining and underfill operations of the assembly process. Solder joining of the die and substrate and curing of the underfill material between the die and substrate is accomplished in the same heating and cooling operation. As a result, the coefficient of thermal expansion (CTE) mismatch stresses incurred prior to application and curing of underfill by a device packaged according to the conventional technique having a separate heating and cooling operation following solder joining, are avoided. These stresses are of particular concern in smaller device size technologies (e.g., 0.13 microns and smaller) using low k dielectrics and large die sizes due the difference in CTP between the die and substrate.