Array of transistors with low voltage collector protection

Abstract

An array ( ) of transistors ( ) formed in a p-type layer ( ), and including a second heavily doped p-type region ( ) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region ( ) is formed in the p-type layer ( ) and proximate a n-type buried layer ( ) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region ( ) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring ( ) collects the minority carriers (T ) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.