The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2004

Filed:

Mar. 26, 2003
Applicant:
Inventor:

Jeffrey B. Davis, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 ;
U.S. Cl.
CPC ...
H03B 1/00 ;
Abstract

An apparatus and a method for compensating the drain current degradation in pMOS transistors are disclosed. The pMOS transistor receiving drain current compensation is a primary pMOS transistor. The apparatus comprises of a plurality of pMOS transistors subject to drain current degradation correlating to drain current degradation of the primary pMOS transistor, at least one compensation pMOS transistor coupled in parallel with the primary pMOS transistor, and an output voltage decoder to activate one or more of the compensation pMOS transistors to compensate for the drain current degradation of the primary pMOS transistor based on monitored drain current degradation of the plurality of pMOS transistors.


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