The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2004
Filed:
Jun. 25, 2002
Applicant:
Inventor:
Peter Hagemeyer, Dresden, DE;
Assignee:
Infineon Technologies AG, , DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9792 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
U.S. Cl.
CPC ...
H01L 2/9792 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ;
Abstract
A vertical transistor ( ) has a source region ( ), a drain region ( ), a gate region ( ), and a channel region ( ) between the source region ( ) and the drain region ( ), which are arranged in a vertical direction in a semiconductor substrate ( ), the gate region ( ) having an electrical insulation from the source region ( ), from the drain region ( ) and from the channel region ( ) and being arranged around the channel region ( ) in such a way that the gate region ( ) and the channel region ( ) form a coaxial structure.
Quick Actions:
Hagemeyer, Peter. (2004). Vertical transistor, memory arrangement and method for fabricating a vertical transistor (U.S. Patent No. 6768166). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6768166
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile